CEO寄语

2017-01-01 上海/北京/美国硅谷 1


最值得骄傲的是我们拥有正在不断扩大的世界级人才团队,这是我们继续前行的核心基础。我们在全球三个科技重镇-上海、北京和美国硅谷建立"联合实验室"和研发中心的根本目的是打造我们的人才体系。于我们而言,只有拥有优秀的人才,才能把事情做成,做好,才有可能精益求精。只有扎扎实实把我们的技术和产品做好,给市场和客户带来价值,我们这个团队和企业的价值才得以体现,我们团队中的每一位成员的自我价值也得以实现。所以,挑剔的客户、领先的技术和优质的产品,才是我们生存的核心价值。

 


Digital/ASIC Design Engineer

2017-07-27 Shanghai/Beijing 3 Negotiable


Job Description:

1.  This position is for a digital/ASIC design engineer to build next-generation analog/digital mixed SoC chips.

2.  Handling every aspect in ASIC design flows including: architecture, RTL coding, Verification, Synthesis, DFT, STA and P&R.

3.  Participate into the chip debug and validation.

Qualifications:

1.  BSEE with minimum 3-year of working experience or MSEE with minimum 1-year of working experience for starting position

2.  MSEE with minimum 3-year of working experience for senior position.

3.  Excellent knowledge for ASIC design, such as MOS transistor, arithmetic structure (addition, multiplication), timing analysis, design for test, meta-stability and etc.

4.  Need fundamental understanding for digital signal processing, such as FIR/IIR filter structure, error correction, decimation and etc.

5.  Usage experience (not all of them required) of industry-standard EDA tools, such as VCS/NC, Design Compiler, Primetime, Formality/Conformal and Tetramer/DFT compiler.

6.  Experience in bus design (I2C, AHB or AIX), data path design (Filter, correlation or Condic) and logic control (PCS or MAC) will be a plus.

7.  Experience in metrics driven verification methodology (system Verilog/UVM based) will be a plus.

8.  Experience in every aspect of ASIC design will be a great plus.


You will be reporting to the Director of Digital Design. 

We offer you an opportunity to work and develop yourself in the growing high-tech company, competitive salary with generous stock options. As well as, we invite you to a challenging position supported by our international team of professionals.

Please send your application to jobs@photonic-tech.com with a title “Digital/ASIC Design Engineer”.



Senior Analog/RF Layout Design Engineer

2017-07-27 Shanghai/Beijing 2 Negotiable


Job Description:

You will optimize the layout and high-frequency (multi-gigahertz) routing of high-precision analog circuits, such as:

1.  High-speed amplifiers, wireline SERDES, PLL, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc. 

2.  Use EDA tools (Cadence, Mentor, Allegro) to layout, extract, and verify the high-performance layout.

3.  Work and iterate with analog/RF design engineers to optimize the layout performance.

Qualifications:

1.  BSEE in analog IC design with 8+ years’ experience.

2.  Expert level experience in Cadence EDA tools.

3.  Team player with good communication skills.

4.  Desired: Experience with the layout of SERDES transmitter/receiver, PLL, TIA, CDR, LNA etc.

5.  Desired: Experience in RF circuit layout, including high-frequency effects, crosstalk, and bandwidth optimization.

6.  Desired: Experience in chip top level integration and verification.


You will be reporting to the Layout Manager. 

We offer you an opportunity to work and develop yourself in the growing high-tech company, competitive salary with generous stock options. As well as, we invite you to a challenging position supported by our international team of professionals.

Please send your application to jobs@photonic-tech.com with a title “Senior Analog/RF Layout Design Engineer”.


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