2017/01/01 Shanghai/Beijing/Silicon Valley Several
We are a Shanghai/Silicon-Valley based stealth-mode semiconductor startup, A-Round and B-Round VC-backed by Walden International -- one of the world’s leading venture capital firm for semiconductors. We develop highly-integrated photonic-electronic solutions for high-growth industries such as optical networking and next-generation IOT systems. Optical-ICs is one of the hottest areas today, due to the “Optical Supercycle” -- Big-Data and China.
Our returnee founders are successful entrepreneurs with backgrounds from Stanford, Oregon-State, Fudan, Intel, LSI and NVidia. They have been involved in six successful startups, with their last IC startup in Shanghai previously acquired for 8.5x return in < 5 years.
Our company culture is like a Silicon-Valley startup, with a unique USA/China blend of innovation. Our vision is to learn, challenge, and grow, creating exponential value for our customers, ourselves, and our company.
NOW is the golden-age for ICs in China – seize it!
2017/07/27 Shanghai/Beijing 3 Negotiable
1. This position is for a digital/ASIC design engineer to build next-generation analog/mixed-signal SoC chipsets.
2. Handle many aspects of ASIC design flow including: architecture, RTL coding, Verification, Synthesis, DFT, STA and P&R (for back-end design).
3. Participate in chip debug, validation, and marketing specifications.
1. BSEE with minimum 3-year experience or MSEE with minimum 1-year experience of digital experience.
2. Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication), timing analysis, DFT, meta-stability, finite state machines.
3. Fundamental understanding of digital signal processing, such as FIR/IIR filter structure, error correction, integration/averaging, and decimation.
4. Desired usage experience of mainsteam industry-standard EDA tools, such as VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
5. Experience in several vertical aspects of ASIC design (front-end and back-end) will be a great plus.
6. Experience in bus design (I2C, AHB/APB/AXI), datapath design (Filter, correlation or Cordic) and logic control (PCS or MAS) is a plus.
7. Experience with CMOS image sensors (digital-design) such as MIPI, readout, and timing control, is a plus.
8. Experience in metrics-driven verification methodology (System-Verilog/UVM based) is a plus.
9. Experience in mixed-signal SOC design is a plus.
10.Experience in perl/python/tcl scripts is a plus.
You will be reporting to the Director of Digital Design.
We offer you an opportunity to work and develop yourself in the growing high-tech company, competitive salary with generous stock options. As well as, we invite you to a challenging position supported by our international team of professionals.
Please send your application to email@example.com with a title“Digital/ASIC Design Engineer”.