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Senior Analog/RF Layout Design Engineer

  • 招聘人数2
  • 工作地点Shanghai/Beijing
  • 工资待遇Negotiable
  • 发布日期2017-07-27
  • 有效期不限

职位描述

Job Description:

You will optimize the layout and high-frequency (multi-gigahertz) routing of high-precision analog circuits, such as:

1.  High-speed amplifiers, wireline SERDES, PLL, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc. 

2.  Use EDA tools (Cadence, Mentor, Allegro) to layout, extract, and verify the high-performance layout.

3.  Work and iterate with analog/RF design engineers to optimize the layout performance.

Qualifications:

1.  BSEE in analog IC design with 8+ years’ experience.

2.  Expert level experience in Cadence EDA tools.

3.  Team player with good communication skills.

4.  Desired: Experience with the layout of SERDES transmitter/receiver, PLL, TIA, CDR, LNA etc.

5.  Desired: Experience in RF circuit layout, including high-frequency effects, crosstalk, and bandwidth optimization.

6.  Desired: Experience in chip top level integration and verification.


You will be reporting to the Layout Manager. 

We offer you an opportunity to work and develop yourself in the growing high-tech company, competitive salary with generous stock options. As well as, we invite you to a challenging position supported by our international team of professionals.

Please send your application to jobs@photonic-tech.com with a title “Senior Analog/RF Layout Design Engineer”.

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