Analog Design Engineer 模拟设计工程师

Responsibilities:

1.You will design, analyze, and implement high-performance (>10GHz) PLL, wireline amplifiers, CDR, SERDES, PLL, PAM4, TDCs, TOF, low-noise amplifiers, transmitters, power-amplifiers and power-drivers, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.

2.Use EDA tools (Cadence, Mentor) to run simulation and function verification.

3.Guide layout engineer to optimize layout. 

4.Chip debug and testing individually and with the team.

5.Other tasks assigned by line manager.

Qualifications:

1. MSEE in analog IC design. 
2. Hands-on design experience with multi-gigahertz SERDES transmitter/receiver, TIA, PLL, CDR, LNA, ToF, Temperature Sensor, power management IC or low-speed ADC/amplifier.
3. Great team management skills.

4. Experience in Cadence EDA tools.
5. Team player with good communication skills.

Location: Shanghai, Shenzhen

要求：电子工程硕士，2年以上模拟电路设计，擅长SerDes等高速接口，TIA, PLL, CDR, LNA, ToF, Temperature Sensor, PMIC(DC-DC Boost/Buck) 低速ADC/放大器等任一领域。欢迎应届硕士、博士。